Publications

Full list in Google Scholar

Journal Publications

• [TIFS’23] Tan, Weihang, Sin-Wei Chiu, Antian Wang, Yingjie Lao, and Keshab K. Parhi. “PaReNTT: Low-Latency Parallel Residue Number System and NTT-Based Long Polynomial Modular Multiplication for Homomorphic Encryption.” in IEEE Transactions on Information Forensics and Security (2023), doi: 10.1109/TIFS.2023.3338553.
• [TC’23] Tan, Weihang, Antian Wang, Xinmiao Zhang, Yingjie Lao, and Keshab K. Parhi. “High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography.” IEEE Transactions on Computers (2023).
• [TCAS-I’21] Antian Wang, Tan, Weihang, Yuejiang Wen, and Yingjie Lao. “NoPUF: A novel PUF design framework toward modeling attack resistant PUFs.” IEEE Transactions on Circuits and Systems I: Regular Papers 68, no. 6 (2021): 2508-2521.
• [TCAS-II’21] Tan, Weihang, Benjamin M. Case, Antian Wang, Shuhong Gao, and Yingjie Lao. “High-speed modular multiplier for lattice-based cryptosystems.” IEEE Transactions on Circuits and Systems II: Express Briefs 68, no. 8 (2021): 2927-2931. Code
• [JSPS’21] Tan, Weihang, Benjamin M. Case, Gengran Hu, Shuhong Gao, and Yingjie Lao. “An ultra-highly parallel polynomial multiplier for the bootstrapping algorithm in a fully homomorphic encryption scheme.” Journal of Signal Processing Systems 93 (2021): 643-656.

Conference Publications

• [ICCAD’23] Tan, Weihang, Yingjie Lao, and Keshab K. Parhi. “KyberMat: Efficient Accelerator for Matrix-Vector Polynomial Multiplication in CRYSTALS-Kyber Scheme via NTT and Polyphase Decomposition.” In 2023 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2023.
• [DAC’23] Antian Wang, Bingyin Zhao, Tan, Weihang, and Yingjie Lao, “NNTesting: Neural Network Fault Attacks Detection Using Gradient-Based Test Vector Generation”. In 2023 60th ACM/IEEE Design Automation Conference (DAC), pp. 1-6. IEEE 2023
• [DFT’22] Antian Wang, Tan, Weihang, Keshab K. Parhi, and Yingjie Lao. “Integral Sampler and Polynomial Multiplication Architecture for Lattice-based Cryptography.” In 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 1-6. IEEE, 2022.
• [AsianHOST’21] Tan, Weihang, Antian Wang, Yingjie Lao, Xinmiao Zhang, and Keshab K. Parhi. “Pipelined high-throughput NTT architecture for lattice-based cryptography.” In 2021 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), pp. 1-4. IEEE, 2021.
• [ISVLSI’20] Tan, Weihang, Antian Wang, Yunhao Xu, and Yingjie Lao. “Area-efficient pipelined vlsi architecture for polar decoder.” In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 352-357. IEEE, 2020.
• [SiPS’19] Tan, Weihang, Aengran Au, Benjamin Aase, Shuhong Aao, and Yingjie Lao. “An efficient polynomial multiplier architecture for the bootstrapping algorithm in a fully homomorphic encryption scheme.” In 2019 IEEE International workshop on signal processing systems (SiPS), pp. 85-90. IEEE, 2019.

Patent

Three patents are currently either in the filing or review process.

• Keshab K. Parhi, Xinmiao Zhang, Tan, Weihang, Antian Wang and Yingjie Lao., Regents of the University of Minnesota, Ohio State Innovation Foundation and Clemson University Research Foundation, 2023. LOW-LATENCY POLYNOMIAL MODULO MULTIPLICATION OVER RING. U.S. Patent Application 17/582,560.
• Keshab K. Parhi, Tan, Weihang, Sin-Wei Chiu, Antian Wang, and Yingjie Lao, Parallel polynomial modular multiplication using NTT and inverse NTT, U.S. Patent Application 18/500,670, Nov. 2, 2023

Recent Accepted Papers

(To be updated)

Preprint Papers

(To be updated)